As is well known, the ever increasing size and complexity of electronic non-volatile memory devices monolithically integrated on a semiconductor has created a demand for several internal circuit blocks to be rendered fully visible and accessible from the device terminals.
This demand descends from the need to have the data streams, controls and functions suitably set up to facilitate memory surveys, implement analysis features for improved reliability, and reduce the overall size of the memory device.
The demand is also prompted by the fact that the design of certain blocks, their layout or timing, may have to be checked at the initial stages of their fabrication. It can be appreciated that such testing would be facilitated if an ability to view and inspect each internal block can be ensured by a memory device of suitable design.
In this application field, memories are known which are divided into two sub-matrices, hereinafter referred to as the upper (UP) and lower (DOWN) sub-matrices, each) associated with a corresponding row decoder UP.sub.-- ROW.sub.-- DEC and DW.sub.-- ROW DEC.
A column or bit line selector BL is provided on one side of the matrix. On that same side, sequentially connected sense amplifiers SA and output stage buffers OUT are also provided.
In a memory of this type, there are two distinct signal paths between the input/output terminals I/O and the column selector. A first path is dedicated to reading operations from the memory, and the second path is dedicated to the transfer of programmed data within the memory.
Another major feature of this conventional memory architecture is that no normal data transmission path is provided between one side of the memory, such as the side where the address terminals are usually located, for example, and the other side thereof, i.e., the side where the output stages are accommodated.
In this kind of memory, testing is usually allowed by some dedicated circuitry.
The provision of test-dedicated circuitry obviously involves considerable designing effort, takes up circuit area, and increases costs.
In addition, interconnection lines must be provided between circuit nodes which may be far apart. These lines occupy substantial circuit area and require for their activation a complicated dedicated control network of non-modular nature.
In fact, the transmission of data picked up from the memory matrix for reading and sending to the output terminals is effected on dedicated lines; and this applies as well to the transmission of data indicating the memory states and running events. Thus, auxiliary lines must be provided for the testing data which extend through the memory device, according to the locations of the internal and external sources from which data and information are to be picked up.
It should also be considered that certain tests require a monitoring signal, additional to a control signal, which increases the total number of test signals and the complexity of the arrangement.
In this way, in view of the continually increasing amount of information about the memory operation which must be sent out, a large number of extra lines must be added to the memory data transmission lines, thereby increasing the area physically occupied by the memory device and making the device more complicated to exercise.
Furthermore, a testing circuitry designed for a specific circuit architecture cannot be readily adapted for other circuit types or new products, even if partaking much of their design.
Summarized in FIG. 2 are schematical representations of the main timing signals which are typical for a memory architecture of the above type.
These signals can be described as follows.
ATDn--signal which detects a transition on one of the address inputs. This detection would initiate a read cycle.
PC--R a signal which activates all of the devices intended for a precharge function.
EQ--a signal which equalizes the output nodes of the sense amplifiers SA and enables the reading of data from the memory.
LOAD--R a signal for transferring newly read data to those output buffer stages which are normally disconnected from the rest of the internal circuitry.
In this conventional type of architecture, each circuit block has a dedicated line or bus. For example, some signals in FIG. 2 show that only one predetermined line at a time is enabled to transfer output data. This means that the various blocks are not necessarily active at all cycles, and yet much of the circuit area is taken up by the various connection lines and related control circuits.